Implementation of SDRAM controller By Verilog Hardware Description Language

碩士 === 國立臺北科技大學 === 電機工程研究所 === 103 === This thesis focuses on the extension of SRAM(Static Random Access Memory). Firstly, We propose a SDRAM controller to instead of SRAM extension on the ARM system. This is the SRAM extension in replaced with the SDRAM controller which is implemented with SDRAM....

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Bibliographic Details
Main Authors:	WU, TAI-YU, 吳岱祐
Other Authors:	宋國明
Format:	Others
Language:	zh-TW
Published:	2015
Online Access:	http://ndltd.ncl.edu.tw/handle/crfhnk

id	ndltd-TW-103TIT05442044
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spelling	ndltd-TW-103TIT054420442019-06-29T05:34:43Z http://ndltd.ncl.edu.tw/handle/crfhnk Implementation of SDRAM controller By Verilog Hardware Description Language 以Verilog硬體描述語言實現同步動態隨機存取記憶體控制器 WU, TAI-YU 吳岱祐碩士國立臺北科技大學電機工程研究所 103 This thesis focuses on the extension of SRAM(Static Random Access Memory). Firstly, We propose a SDRAM controller to instead of SRAM extension on the ARM system. This is the SRAM extension in replaced with the SDRAM controller which is implemented with SDRAM. Secondly, the Modelsim software is selected to complete the simulation of SDRAM controller. The operating frequence of 166MHz and the operating voltage of 3.3 voltage are considered for SDRAM input/output interface. Notify that the SDRAM can not work in precharge time. This thesis provides a Bank method to resolve this problem by accessing a temporary memory in the precharge time. After the precharge ,the missed data will be recover in SDRAM. The Verilog HDL is used not only to complete the simution but also to verify the function of SDRAM. Finally, the DDR SDRAM specification will be confirmed that the proposed SDRAM controller works correctly. 宋國明 2015 學位論文 ; thesis 0 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立臺北科技大學 === 電機工程研究所 === 103 === This thesis focuses on the extension of SRAM(Static Random Access Memory). Firstly, We propose a SDRAM controller to instead of SRAM extension on the ARM system. This is the SRAM extension in replaced with the SDRAM controller which is implemented with SDRAM. Secondly, the Modelsim software is selected to complete the simulation of SDRAM controller. The operating frequence of 166MHz and the operating voltage of 3.3 voltage are considered for SDRAM input/output interface. Notify that the SDRAM can not work in precharge time. This thesis provides a Bank method to resolve this problem by accessing a temporary memory in the precharge time. After the precharge ,the missed data will be recover in SDRAM. The Verilog HDL is used not only to complete the simution but also to verify the function of SDRAM. Finally, the DDR SDRAM specification will be confirmed that the proposed SDRAM controller works correctly.
author2	宋國明
author_facet	宋國明 WU, TAI-YU 吳岱祐
author	WU, TAI-YU 吳岱祐
spellingShingle	WU, TAI-YU 吳岱祐 Implementation of SDRAM controller By Verilog Hardware Description Language
author_sort	WU, TAI-YU
title	Implementation of SDRAM controller By Verilog Hardware Description Language
title_short	Implementation of SDRAM controller By Verilog Hardware Description Language
title_full	Implementation of SDRAM controller By Verilog Hardware Description Language
title_fullStr	Implementation of SDRAM controller By Verilog Hardware Description Language
title_full_unstemmed	Implementation of SDRAM controller By Verilog Hardware Description Language
title_sort	implementation of sdram controller by verilog hardware description language
publishDate	2015
url	http://ndltd.ncl.edu.tw/handle/crfhnk
work_keys_str_mv	AT wutaiyu implementationofsdramcontrollerbyveriloghardwaredescriptionlanguage AT wúdàiyòu implementationofsdramcontrollerbyveriloghardwaredescriptionlanguage AT wutaiyu yǐverilogyìngtǐmiáoshùyǔyánshíxiàntóngbùdòngtàisuíjīcúnqǔjìyìtǐkòngzhìqì AT wúdàiyòu yǐverilogyìngtǐmiáoshùyǔyánshíxiàntóngbùdòngtàisuíjīcúnqǔjìyìtǐkòngzhìqì
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Implementation of SDRAM controller By Verilog Hardware Description Language

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