| Summary: | 碩士 === 國立虎尾科技大學 === 電機工程研究所 === 103 === This study used a System-On-Programming-Chip (SOPC) method and a development platform with a Field-Programmable-Gate-Array (FPGA) to develop a passive automatic focus control system. A 32-bit processor was established as the system control center within the FPGA, with hardware modules for control the motor movement and for processing images to achieve autofocus, In addition, the modularity of the design improved the flexibility of the system during development and porting.
The motor control loop contained Proportional-Derivative (PD) and Proportional -Integral (PI) controllers for controlling position and speed, respectively. In addition, the Constant Sample-time Digital Tachometer (CSDT) method was used for measuring the motor speed, with the Sum Modulus Difference (SMD) algorithm being employed to calculate the image sharpness. System used twice global search methods as focus strategy.
Finally, we tested three versions of an object to verify the feasibility of the system, thus determining any performance disparity between the SMD software and hardware modules.
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