| Summary: | 碩士 === 國立聯合大學 === 電子工程學系碩士班 === 103 === The study proposes a new safe driving monitoring system and its hardware design verified in real car. It consists of “Driver head leaning detecting subsystem” and “Lane departure detecting subsystem”.
The driver head leaning detecting subsystem is used to monitor driver head leaning. In the subsystem, the IR LED light sources are sited on the back cushion behind the driver’s head, the IR receivers are placed above and in front of the driver’s head to receive IR LED signals, and the detecting algorithm is developed to analyze the signals. By analyzing the changes of the received IR LED signals, driver head leaning can be detected correctly. Its features are as follows. (i) Abnormal leaning of the driver’s head can be detected correctly. (ii) The action of viewing rear-view mirrors is recognized to be normal. (iii) The subsystem cost is cheap. (iv) The design is robust to harsh climate and road environment. (v) The system design is safe to the driver’s eyes. (vi) Because the IR light is invisible, the subsystem doesn’t interfere with the vision of the driver. (iv) It isn’t influenced by the sunglass the driver wears.
In the lane departure detecting subsystem, the CMOS sensor is used to acquire the frames in the driving direction of the vehicle and the lane departure detecting algorithm is developed to analyze the acquired frames. After segmenting the lanes, computing its angles and distances by Hough transformation, detecting and compensating errors, and examining the warning criteria, the algorithm can correctly detect whether the vehicle is departed from the lane. The demonstrations of software simulation on six test videos from different environments indicate the subsystem can detect lane departure successfully. For real-time realization of the proposed lane departure detecting subsystem, we have worked with hardware design of the subsystem for the six different environments, and implemented using the chip of Altera Cyclone® IV EP4CE115 FPGA. The simulation results reveal that the frame-rate of the design is higher than 64 frames/sec with frame size of 480 × 640 under 10846 logic elements (LEs) and 442336 memory-bits in hardware cost being paid.
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