| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 103 === In massive MIMO systems, the number of antennas becomes enormous and would need to be configurable in order to support different applications. This brings great challenges in designing efficient MIMO detector structures.
On the other hand, multicore systems have been widely utilized for achieving high processing throughput and the Network-on-Chip (NoC) paradigm has been recognized an effective means of inter-connecting processing elements in the multicore architecture. This thesis explores the design of MIMO detector for massive MIMO systems based on a multicore system using NoC architectures. First of all, a tree-searching based MIMO detection algorithm is revised to be implemented on the NoC-based multicore processor. The VLSI architecture for the processing elements, routers, and thus the entire NoC structure will be clearly depicted. Moreover, two types of NoC topologies are investigated in order to illustrate the design trade-offs between processing speed and system complexity.
In addition, we will show that the proposed MIMO detector engine is suitable for massive MIMO system that equips with large number of antennas and requires a supporting to the configurability. The FPGA implementation for the proposed NoC-based MIMO detector is presented and experimental results are documented.
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