| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 103 === This thesis is relevant to the hardware/software co-design and implementation of a temporal-median-filter-based algorithmic processing system for background subtraction. The research work consists of the following four parts.
The first part is related to the software design of the temporal-median-filter-based background subtraction algorithm. Meanwhile, through using the image-based output results, this algorithm has demonstrated its superiority in various applications.
The second part is to design and implement a temporal-median-filter-based algorithmic processor for background subtraction. This algorithmic processor comprises three subprocessors which are for image information access, median finding, and background subtraction. Finally, all these parts mentioned above are integrated together and implemented on an Altera FPGA development board.
The third part is related to the design and implementation of an algorithmic processing system which comprises SDRAM (for storing multiple complete images), the algorithmic processor described above, NIOS II CPU, and the related firmware. Meanwhile, the functionality of this system is verified through using NIOS II IDE.
The fourth part is to analyze and evaluate the software, firmware, and hardware performance of the whole algorithmic processing system.
On the whole, the goals of this thesis are to do research on a temporal-median-filter-based background subtraction algorithm and design an algorithmic processing system (on an Altera FPGA development board) for it. After being verified with various kinds of digital images, the algorithmic processing system developed in this thesis has shown fabulous computing performance and the related hardware/software co-design method can also be used to improve the efficiency of the design and verification process for other algorithmic processing systems.
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