| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 103 === Firstly, this thesis presents an ultra wide locking range divide-by-5 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process . The ILFD circuit is realized with a cross-coupled n-core MOS dual-resonance RLC-tank oscillator with linear mixer to extend the locking range. The core power consumption of the ILFD core is 8.38 mW. The divider’s free-running frequency has dual-bands at 3.10 and 2.81 GHz by switching the varactor’s control bias, At the incident power of 0 dBm, the locking range is 4.4 GHz (32.35%), for the incident frequency extending from 11.4 to 15.8 GHz.
The second circuit is a wide locking range divide-by-5 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process . The ILFD circuit is realized with a capacitive cross-coupled n-core MOS dual-resonance RLC-tank oscillator with linear mixer to extend the locking range. The core power consumption of the ILFD core is 8.38 mW. The ILFD uses a single injection MOSFET. At the incident power of 0 dBm, the locking range is 2.8 GHz (19.7%) for the incident frequency extending from 12.8 to 15.6 GHz.
Finally, an ultra wide locking range divide-by-4 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The ILFD circuit is realized with a cross-coupled n-core MOS dual-resonance RLC-tank oscillator with linear mixer to extend the locking range. The core power consumption of the ILFD core is 11.872 mW. The divider’s free-running frequency has dual-bands at 2.87 and 2.69 GHz by switching the varactor’s control bias, At the incident power of 0 dBm the locking range is 3.2 GHz (28.82%), for the incident frequency extending from 9.5 to 12.7GHz.
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