| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 103 === With the advent of semiconductor technology, a large number of IP blocks can be integrated into a single chip. Unfortunately, in such a multicore SoC system, the bus-based architecture may become the bottleneck of system performance. To overcome this, the NoC-based architecture has been proposed in the past decade.
To demonstrate this architecture, a NoC-based architecture for implementing Fast Fourier Transform (FFT) is proposed in this thesis. The architecture consists of preprocessors, routers, network interfaces, and processing elements. To make the router efficient, pipeline technique and wormhole switching are used with the XY routing algorithm. In addition, a method of data scheduling and distributing is developed to increase the load balancing and efficiency of packet distribution of the data sequence requirement of the FFT. The processing element adopts the Radix-22 algorithm and uses CORDIC to replace the traditional complex multiplier. Moreover, the meshbased network is fully parameterized to make it flexible.
Various sizes, including 2 × 2, 4 × 4, and 8 × 8, with 256 points capability, of the NoC-based architecture have been implemented and verified on a Xilinx Virtex- 6 device and the TSMC 0.18-μm cell library. The core area of the 8 × 8 NoC architecture is 11,302.26 μm × 11,300.16 μm, equivalent to 8,099,544 gates. The average power consumption is 2693.4 mW at the operating frequency of 66 MHz.
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