A 12-bit 5MS/s Fully Differential SAR ADC Chip Design with Hybrid Resistor-Capacitor Array DAC Technique
碩士 === 國立臺灣科技大學 === 電子工程系 === 103 === This thesis presents a 1.8-V 12-bit 5MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in the TSMC 1P6M 1.8V 0.18-um CMOS process. By applying a hybrid resistor-capacitor DAC that reduces DAC switching energy and the area...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/29719351441611433909 |