| Summary: | 碩士 === 國立臺灣大學 === 電信工程學研究所 === 103 === Phase noise is an important parameter to evaluate a frequency synthesizer. It not only represents the degree of purity of output signal, but also can be utilized to predict the effect on signal interaction between two neighboring channels. In regard to some specific systems, such as RF receiver and optical clock-data recovery circuits, out-of-band phase noise dominates the sensitivity and bit error rate (BER) of these systems. Out-of-band phase noise is produced by phase noise of voltage-controlled oscillators (VCOs) and quantization noise of delta-sigma modulator (DSM). Therefore, reducing the phase noise of VCOs and the quantization noise of DSM can improve the out-of-band phase noise of a frequency synthesizer. In this thesis, two circuits are discussed. First one is inserting resistors into the dc path of the VCO to improve phase noise. Another one is utilizing the phase interpolator to reduce the quantization noise of DSM and then the phase noise can be improved.
The first circuit is focused on inserting resistors into the path of direct current of the VCO. Thus the period in saturation region is decreased and the production of flicker noise of the transistors is reduced as well. Finally, the out-of-band phase noise of VCOs can be improved. The VCO is operated at 19.15-22.78 GHz. It includes a modified complementary LC-VCO, a 3-stage current mode logic (CML) divider, and a differential-to-single (D2S) circuit. The VCO phase noise at 1-MHz offset frequency is -98.4 dBc/Hz. Its output power is -3.8 dBm. The power consumption of VCO is 2.9 mW, and the power consumption of buffers is 8 mW. The chip size is 0.335 mm2. It is fabricated by TSMC 90-nm CMOS technology.
The second part of this thesis is focused on utilizing phase interpolator (PI) to reduce minimum phase jump, which has a critical effect on quantization noise. One period of input signal of PI is divided equivalently into 32 parts. Therefore, the minimum phase jump has decreased 32 times. Consequently, the quantization noise of DSM can be reduced as well. This circuit is used to implement a 3.65 GHz fractional-N frequency synthesizer and which includes a complementary LC-VCO, a 2-stage CML divider, a dual-reference interpolator (DI), DI controller (DC), a 5-stage 2/3 divider cell (23Cell), a delta-sigma modulator (DSM), a phase frequency detector (PFD), a charge pump (CP), and a 2nd low pass filter (2nd LPF). The reference frequency is 26 MHz and the loop bandwidth is 66.7 kHz. The phase noise at 1-MHz offset frequency is -115.5 dBc/Hz. The output power is -3.57 dBm, and the total dc consumption is 54.7 mW. It is fabricated by TSMC 180-nm CMOS technology, and the chip size is 0.43 mm2.
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