| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 103 === Analog-to-digital (A/D) converters which have been a communicator between the analog world and digital domain are indispensable building block in many systems.
In this dissertation, a 10-bit 400-MS/s pipeline ADC is proposed to achieve low power in a 90-nm CMOS technology. On the other hand, amplifiers, important and indispensable block of pipeline ADCs, consume significant power to ensure the performance. A prior art [1] employing a single-stage amplifier consisting of a NMOS differential pair with a PMOS load in pipeline ADCs has been proved that amplifier can provide better conversion-efficiency while achieving better FoM. Although the amplifier increases the power-efficiency, it also introduces the ineluctable linearity issue. A multi-bit front-end stage is a straightforward solution but the solution increases the number of comparators and makes the front-end stage more sensitive to the offset. Hence, this work proposes a coarse-stage-assisted front-end stage that not only resolves 4.5-bit in the first stage but also reduces the number of comparators and becomes less sensitive to the offset.
The proposed ADC has been fabricated in a 90-nm standard CMOS technology which occupies 0.15mm2. The proposed ADC consumes 8.7 mW from a 1-V supply and achieves an SNDR of 57.23 dB at a 5.1-MHz input and 55.95 dB near Nyquist rate. It also achieves a signal-to-noise-plus-distortion (SNDR) better than 55 dB over the entire Nyquist band. The figure-of-merit (FoM) of the proposed ADC is 42 fJ/Conv.
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