| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 103 === Transistor scaling down has been the principal factor in driving CMOSFET performance improvement for more than thirty years. As transistor scales down, reduction of dynamic switching power (fCVDD2) is required, in concern of power consumption and heat dissipation issue. Transistor operating frequency and capacitance cannot be lowered, in pursuit of higher speed and on current. Therefore, lowering Vdd is the solution to reduce the dynamic switching power as technology nodes progress.
In transistor design, IOFF should remain the same or become even lower to maintain low static power (IOFFVDD), and ION shouldn’t be lower for the sake of delay. As a result, devices with steep subthreshold slopes are desired. However, traditional transistor subthreshold slope is limited at 60 mV/decade due to its thermionic emission transport mechanism. To break through the limit, steep-slope devices with subthreshold slope smaller than 60 mV/decade are required.
Candidates of steep-slope devices include Negative Capacitance FET (NCFET), Tunneling FET (TFET), Nanoelectromechanical relay (NEM relay), and Impact-ionization MOS (IMOS). While TFET suffers from low on current, IMOS suffers from high operating voltage and reliability issue due to its breakdown transport mechanism, and NEM relay suffers from large hysteresis loop and low speed on switching. NCFET stands to be the promising steep-slope device among the candidates. Though traditional NCFET may have hysteresis loop in seek of steep SS, the hysteresis loop can still be eliminated by some novel structure designs of NCFET proposed in the thesis.
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