Implementation of High-Resolution and Area-Efficient FPGA Programmable Delay Lines

Implementation of High-Resolution and Area-Efficient FPGA Programmable Delay Lines

碩士 === 國立臺灣大學 === 電子工程學研究所 === 103 === In this work, the high area-efficient and high-resolution programmable delay line that can be implemented on FPGA is proposed. We also proposed high area-efficient delay cells based on FPGA architecture. Using the different characteristics of these delay cells...

Full description

Bibliographic Details
Main Authors: Chia-An Lee, 李家安
Other Authors: Jiun-Lang Huang
Format: Others
Language:en_US
Published: 2015
Online Access:http://ndltd.ncl.edu.tw/handle/00619650833227534348
id ndltd-TW-103NTU05428101
record_format oai_dc
spelling ndltd-TW-103NTU054281012016-11-19T04:09:56Z http://ndltd.ncl.edu.tw/handle/00619650833227534348 Implementation of High-Resolution and Area-Efficient FPGA Programmable Delay Lines 基於現場可程式邏輯閘陣列之高解析度與高面積效率延遲線之實現 Chia-An Lee 李家安 碩士 國立臺灣大學 電子工程學研究所 103 In this work, the high area-efficient and high-resolution programmable delay line that can be implemented on FPGA is proposed. We also proposed high area-efficient delay cells based on FPGA architecture. Using the different characteristics of these delay cells to construct the desired programmable delay line. Compared to previous works, our method is 5 to 25 times more efficient in resource usage. However, it costs too much time to measure all delay values. To save time, we only measure partial delay values and use the proposed generation program to predict all delay values. Then, using the proposed selection program to select the desired delay values. To automatically measure delay values, we develop the LabVIEW program which can control the PXI FPGA Carrier and the oscilloscope at the same time. The measurement results show that the proposed programmable delay line achieves 50 ps resolution with 11.1 ns dynamic range. The power consumption is 1 mW. Jiun-Lang Huang 黃俊郎 2015 學位論文 ; thesis 55 en_US
collection NDLTD
language en_US
format Others
sources NDLTD
description 碩士 === 國立臺灣大學 === 電子工程學研究所 === 103 === In this work, the high area-efficient and high-resolution programmable delay line that can be implemented on FPGA is proposed. We also proposed high area-efficient delay cells based on FPGA architecture. Using the different characteristics of these delay cells to construct the desired programmable delay line. Compared to previous works, our method is 5 to 25 times more efficient in resource usage. However, it costs too much time to measure all delay values. To save time, we only measure partial delay values and use the proposed generation program to predict all delay values. Then, using the proposed selection program to select the desired delay values. To automatically measure delay values, we develop the LabVIEW program which can control the PXI FPGA Carrier and the oscilloscope at the same time. The measurement results show that the proposed programmable delay line achieves 50 ps resolution with 11.1 ns dynamic range. The power consumption is 1 mW.
author2 Jiun-Lang Huang
author_facet Jiun-Lang Huang
Chia-An Lee
李家安
author Chia-An Lee
李家安
spellingShingle Chia-An Lee
李家安
Implementation of High-Resolution and Area-Efficient FPGA Programmable Delay Lines
author_sort Chia-An Lee
title Implementation of High-Resolution and Area-Efficient FPGA Programmable Delay Lines
title_short Implementation of High-Resolution and Area-Efficient FPGA Programmable Delay Lines
title_full Implementation of High-Resolution and Area-Efficient FPGA Programmable Delay Lines
title_fullStr Implementation of High-Resolution and Area-Efficient FPGA Programmable Delay Lines
title_full_unstemmed Implementation of High-Resolution and Area-Efficient FPGA Programmable Delay Lines
title_sort implementation of high-resolution and area-efficient fpga programmable delay lines
publishDate 2015
url http://ndltd.ncl.edu.tw/handle/00619650833227534348
work_keys_str_mv AT chiaanlee implementationofhighresolutionandareaefficientfpgaprogrammabledelaylines
AT lǐjiāān implementationofhighresolutionandareaefficientfpgaprogrammabledelaylines
AT chiaanlee jīyúxiànchǎngkěchéngshìluójízházhènlièzhīgāojiěxīdùyǔgāomiànjīxiàolǜyánchíxiànzhīshíxiàn
AT lǐjiāān jīyúxiànchǎngkěchéngshìluójízházhènlièzhīgāojiěxīdùyǔgāomiànjīxiàolǜyánchíxiànzhīshíxiàn
_version_ 1718395069019455488

Similar Items