| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 103 === Two works are discussed in this thesis. The first work is a low-power continuous-time delta-sigma modulator, which consists of a 3rd-order feed-back and feed-forward combined loop filter structure, a 6-bit quantizer with 2 bits truncated by a truncator and embedded with a noise-shaping mechanism. The second work presents an 8-bit noise-shaped SAR ADC, which improves the resolution of the data converter.
A 6-bit, low-power continuous-time delta-sigma modulator (CTDSM) embedded with a noise-shaped and truncated SAR quantizer is proposed in the first work. The bit truncation reduces the number of feedback DAC cells and relaxes the implementation of DEM circuit. The truncation process is embedded in the SAR quantizer which will not degrade the operation frequency of the modulator. Implemented in a 90-nm CMOS process, the measured performance shows a peak SNDR of 65 dB over a signal bandwidth of 3.5 MHz with 110 MHz sampling frequency. This modulator consumes a total power of 3.8 mW, resulting in an FoM of 350 fJ/Conversion-Step.
In second work, a low-power 8-bit noise-shaped SAR ADC is discussed. The proposed ADC gives first-order noise-shaping to the modulator, resulting in an 8-bit 1st-order delta-sigma modulator. This method has the opportunity to extend to higher-order noise-shaping using only one operational amplifier with the help of finite impulse response (FIR) filter. This modulator was realized in a 90-nm CMOS process. Under a power supply of 1.2 V and a sampling frequency of 50 MHz, the measured performance shows a peak SNR and SNDR of 56 dB and 49.8 dB, respectively, over a signal bandwidth of 3.2 MHz. The modulator consumes a total power of 1.5 mW.
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