Power-Supply-Noise-Aware Test Pattern Analysis and Regeneration for Yield Improvement

• Main Authors: Cheng-Yu Han, 韓承佑
• Other Authors: Chien-Mo Li
• Format: Others
• Language: en_US
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/30216520221546924613

碩士 === 國立臺灣大學 === 電子工程學研究所 === 103 === This thesis propose a power-supply-noise-aware test pattern analysis and regeneration framework. The proposed framework analysis timing with reasonable accuracy at much faster speed than existing tools. This technique is very scalable because it is based on linear analytical functions, instead of solving nonlinear functions. Moreover, the function is technology dependent, so there is no need to perform spice characterization for each cells. The experimental results show, for small circuits, the error is less than 5% compared with HSPICE. For large circuits, we achieved 272 times speed up compared with NANOSIM. We perform timing analysis on a 638K gate benchmark circuit to identify 88 timing-violation test patterns (out of 31K test patterns) that are difficult to detect by traditional techniques. After test pattern regeneration, we removed all risky patterns, without fault coverage loss and with only little test inflation. The proposed technique generates shorter test sets and higher fault coverage than commercial power-aware ATPG.