Digital Signal Processing and Architecture Design of Smart Badge Access Point Receiver

• Main Authors: Wen-Yi Lin, 林文一
• Other Authors: 曹恒偉
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/23532176770326517477

碩士 === 國立臺灣大學 === 電子工程學研究所 === 103 === In this thesis we propose a short-distance communication Smart Badge system which communicates through wireless channel and integrates the transceiver into licensed-free 400MHz bands. Modulation format of Smart Badge is DQPSK due to simplicity. The circuit design of Smart Badge is focusing on power saving and long standby time, so it may result in inaccurate carrier frequency and clock frequency, and the receiver is required to tolerate larger offsets. This thesis designs and implements a Smart Badge base station receiver and takes low complexity and low power consumption into main considerations. It achieves a low distortion digital down conversion with down sampling by 428 and transfers the IF signal to baseband for digital signal processing. The receiver has the abilities to detect and compensate max. ±500ppm carrier frequency and clock frequency offset, and also returns amplitude of symbols for automatic gain control circuit to adjust the dynamic range of ADC. BER of fixed-point simulation is 4×〖10〗^(-5)at E_b/N_0=12dB, and the difference between floating-point simulation is less than 0.3dB. Hardware implementation and simulation use TSMC 90nm process offered by CIC, and the receiver after full auto place and route(APR) can operate at 42.8MHz with 0.3mm^2core area and 68.7% area utilization, and the power consumption is 11.7mW.