A Phase Noise Suppression Technique for PLLs with Ring Oscillators

碩士 === 國立臺灣大學 === 電子工程學研究所 === 103 === A frequency synthesizer with a phase noise reduction technique is presented. By the property that the phase noise of an opened-loop delay is smaller than that of a closed-loop delay, an analog delay line is employed to improve the phase noise of a ring oscillat...

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Main Authors: Yi-Han Cheng, 鄭伊涵
Other Authors: Tai-Cheng Lee
Format: Others
Language:zh-TW
Published: 2014
Online Access:http://ndltd.ncl.edu.tw/handle/62887123667889850318
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spelling ndltd-TW-103NTU054280212016-07-02T04:21:18Z http://ndltd.ncl.edu.tw/handle/62887123667889850318 A Phase Noise Suppression Technique for PLLs with Ring Oscillators 降低具環形振盪器之鎖相迴路中相位雜訊的方法 Yi-Han Cheng 鄭伊涵 碩士 國立臺灣大學 電子工程學研究所 103 A frequency synthesizer with a phase noise reduction technique is presented. By the property that the phase noise of an opened-loop delay is smaller than that of a closed-loop delay, an analog delay line is employed to improve the phase noise of a ring oscillator. The proposed phase-locked loop (PLL) can suppress the noise beyond the PLL loop bandwidth. Fabricated in a 0.18μm CMOS technology, for a 32-kHz input frequency, the 1-GHz PLL with a ring oscillator can generate an output with the phase noise -83 dBc/Hz at a 100-kHz frequency offset, which is more than 10 dB suppression. The clock generator consumes 17.64 mW from a 1.8-V power supply. Tai-Cheng Lee 李泰成 2014 學位論文 ; thesis 57 zh-TW
collection NDLTD
language zh-TW
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description 碩士 === 國立臺灣大學 === 電子工程學研究所 === 103 === A frequency synthesizer with a phase noise reduction technique is presented. By the property that the phase noise of an opened-loop delay is smaller than that of a closed-loop delay, an analog delay line is employed to improve the phase noise of a ring oscillator. The proposed phase-locked loop (PLL) can suppress the noise beyond the PLL loop bandwidth. Fabricated in a 0.18μm CMOS technology, for a 32-kHz input frequency, the 1-GHz PLL with a ring oscillator can generate an output with the phase noise -83 dBc/Hz at a 100-kHz frequency offset, which is more than 10 dB suppression. The clock generator consumes 17.64 mW from a 1.8-V power supply.
author2 Tai-Cheng Lee
author_facet Tai-Cheng Lee
Yi-Han Cheng
鄭伊涵
author Yi-Han Cheng
鄭伊涵
spellingShingle Yi-Han Cheng
鄭伊涵
A Phase Noise Suppression Technique for PLLs with Ring Oscillators
author_sort Yi-Han Cheng
title A Phase Noise Suppression Technique for PLLs with Ring Oscillators
title_short A Phase Noise Suppression Technique for PLLs with Ring Oscillators
title_full A Phase Noise Suppression Technique for PLLs with Ring Oscillators
title_fullStr A Phase Noise Suppression Technique for PLLs with Ring Oscillators
title_full_unstemmed A Phase Noise Suppression Technique for PLLs with Ring Oscillators
title_sort phase noise suppression technique for plls with ring oscillators
publishDate 2014
url http://ndltd.ncl.edu.tw/handle/62887123667889850318
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