| Summary: | 碩士 === 國立臺灣大學 === 資訊工程學研究所 === 103 === ABSTRACT
Phase change memory (PCM) is a potential candidate on the storage applications due to its nanosecond-level access latency and byte-addressability. In addition, with the help of multiple-level-per- cell (MLC) technology, PCM could provide comparable capacity to flash memory. However, adopting MLC PCM needs much larger power consumption than SLC PCM. Thus, in this paper, we exploit a SLC/MLC hybrid memory architecture with the proposed pattern-aware write back policy to minimize the energy consumption on the storage devices In addition, we also propose a counter buffer design to reduce the cost on manipulating data structures, and meanwhile, we design a data migration mechanism to migrate data to MLC PCM when the space of SLC PCM is exhausted. We conducted the experiments on the well-known benchmarks and for which the results are encourage.
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