Low-Power Architecture for Multi-Channel NEO and GHA-based Spike Sorting Circuits
碩士 === 國立臺灣師範大學 === 資訊工程學系 === 103 === This research aims to design an implantable spike sorting chip. To minimize possible damage to human brain, the chip area and power consumption specification should be planned carefully. A spike sorting circuit containing spike detection unit and feature extra...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/11674802465706229220 |