| Summary: | 碩士 === 國立臺灣師範大學 === 資訊工程學系 === 103 === This research aims to design an implantable spike sorting chip. To minimize possible damage to human brain, the chip area and power consumption specification should be planned carefully.
A spike sorting circuit containing spike detection unit and feature extraction unit is developed. The spike detection unit implements the Nonlinear Energy Operator (NEO) algorithm, and the feature extraction unit is based on the Generalized Hebbian Algorithm (GHA). This work presents an architecture that shares one calculation unit across all channels, which minimizes area cost and power consumption greatly.
The circuit is implemented on ASIC work flow, which gives extended flexibility on area and power adjustment. The circuit also incoporates clock gating technology so to lower power consumption by memory units.
Last in this paper we present a method for parameter choosing. Based on the parameters chosen, a detailed area and power analysis is given. An analysis on GHA performance is also presented, which proved GHA to be an efficient substitution to the well-known PCA algorithm.
|
|---|
