A Hardware Design of LDPC Coded Modulation Scheme for Flash Memory Applications
碩士 === 國立清華大學 === 通訊工程研究所 === 103 === This thesis is to implement hardware design of LDPC coded modulation with iterative demodulator and decoding system. Demodulator and decoder exchange information in iterative demodulator and decoding system to increase performance of LDPC coded modulation system...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/81394800159687369437 |