A 100MS/s Successive-Approximation Analog-to-Digital Converter with Redundancy

• Main Authors: Lin, Jing Heng, 林敬恆
• Other Authors: Chu, Ta Shun
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/29066498543349448830

碩士 === 國立清華大學 === 電機工程學系 === 103 === The development of Wireless communication technology has greatly improved our lives. 4G communication systems provide high data transmission speeds. It allows people to communicate with high-quality voice or even video calls. Behind the amazing applications, the high speed ADC is an essential block in the system. It’s the only block that can convert the nature signal to digital signal. There many types of ADC keep improving their ability. But the SAR ADC is more popular in recent years, because it takes a lot of advantage of technology scales. In the thesis, we have proposed a high speed SAR ADC with redundancy algorithm. The algorithm combines the criterion of capacitor mismatch and DAC settling time. The radix of each stage can be calculated precisely under 100 million samples per second. The 10 bits SAR ADC is implemented in a TSMC 65 nm CMOS process with 1V supply voltage. The full rail-to-rail input swing is 1.9V peak to peak. This design achieve signal to noise and distortion ratio of 62.09dB, equivalent to the effective number of bits 10.02.The peak DNL values are -0.4 to +0.6 LSB and the peak INL values are -0.4 to +0.63 LSB. The average power consumption is 2.02mW.