| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 103 === Static Random Access Memory (SRAM) is an important circuit in the electronic products owing to the function of high-speed memory. It’s capacity is the main reason for affecting the speed of systems. In order to meet the substantial requirements of stored data, it occupies more and more area in the systems. Hence, the power consumption of SRAM becomes an indispensable issue.
To reduce power consumption of SRAM, lowering the supply voltage is a direct and effective way. Nevertheless, SRAM operating at low VDD would suffer from the following issue : (1) write failure in write operation (2) read disturb in read operation (3) half-select disturb in write operation. Previous work proposes a novel 6T cell with dual-split control (DSC) technique. The word-line (WL) of cell is divided into WLL and WLR. Also, the ground (CVSS) of cell is divided into CVSSL and CVSSR. The feature of cell is pseudo single-ended write with two phases and single-ended read with one phase. It can improve read disturb and half-select disturb by raising CVSS. However, according to the layout and data pattern of cell array, it suffers from ground bounce and the difficulty for raising CVSS.
For ground bounce, we adopt the method proposed by pervious work which is called array-edge memory (AEM) technique. For the other issue, we propose two step charge sharing scheme. In accordance with the data pattern of cell array, loading of CVSS would be different. For the requirement of low power, we employ charge sharing approach. The first step is reset state. At the second step we do the first charge sharing to generate the voltage of CVSS. At the third step, we detect this voltage to decide whether it should be raised again to achieve better performance of cell.
Based on 65nm CMOS logic process, we fabricate a 4Kb SRAM composed of 6T cell with DSC scheme. This work achieves VDDmin equal to 400mV through oscilloscope testing. In addition, VDDmin improvement is 120mV compared with no raising for CVSS.
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