A Low Energy, Area-Efficient, Fast Wakeup Nonvolatile SRAM for Frequent-Off Instant-On Applications

• Main Authors: Lee, Albert, 李岳陞
• Other Authors: Chang, Meng Fan
• Format: Others
• Language: en_US
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/66tafk

碩士 === 國立清華大學 === 電機工程學系 === 103 === Energy-efficient chips, such as wearable and IoT devices, employ SRAM for computing and nonvolatile memory (NVM) for power-off storage to reduce standby current. Unfortunately, this 2-macro (SRAM+NVM) scheme cannot achieve frequent power-off and short BET against SRAM at sleep-mode using a low supply-voltage (VDD), due to large energy usage and slow store (power-off) and restore (power-on) operations, caused by the word-by-word serial transfer of data. Nonvolatile SRAMs (nvSRAM), which perform bit-to-bit data transfer between SRAM and NVM devices within a single cell, are capable of block-level parallel data transfer with faster store/restore operations than are 2-macro schemes. This study proposes a 7T1R nonvolatile SRAM (nvSRAM) to 1) reduce store energy by using a single NVM device, 2) suppress DC-short current during restore operations through the use of a pulsed-overwrite (POW) scheme, and 3) achieves high restore yield by using a differentially supplied initialization (DSI) scheme. This initialization-and-overwrite (IOW) 7T1R nvSRAM improves breakeven-time (BET) by 6+x, compared to previous nvSRAMs. We fabricated a 16Kb IOW-7T1R nvSRAM using HfOx RRAM and a 90nm process. This represents the first ever silicon verified single-NVM nvSRAM macro. Measurements obtained in test-mode confirm that the proposed nvsRAM reduces store energy by 2x and restore energy by 94x, compared to 2R-based nvSRAMs.