| Summary: | 碩士 === 國立清華大學 === 電子工程研究所 === 103 === As the speed of data transmission keeps increasing, traditional copper wire reaches its physical limit, including high loss and high cross talk. In contrast, optical fiber has the characteristics of high bandwidth, low loss, low EMI and low cross talk, which is very suitable for the applications of high speed communications. In recent years, in addition to traditional backbone network, high speed optical communication is gradually applied for commercial electronics products such as USB and HDMI interfaces. Besides, due to the flourishing applications of cloud computing, data centers substantially adopt optical communication as the main technology for data transmission among the servers. Therefore, the future growth and applications of optical communication are expected.
In chapter 2, we will introduce a co-design of transimpedance amplifier and limiting amplifier operated at 10-Gb/s in 90 nm CMOS. Using the topology of regulated cascode (RGC) as the input stage of the transimpedance amplifier, a low input impedance can be obtained thus the bandwidth can be enhanced. Using the design techniques of gain peaking, the limiting amplifier can obtain characteristics of high gain and high bandwidth. Under a supply voltage of 1.5 V, 85 dBΩ transimpedance gain and 9.6 GHz bandwidth are achieved with 130 mW power consumption and a 0.59 mm2 chip area.
In chapter 3, a 40-Gb/s transimpedance amplifier is realized in 90 nm CMOS. It adopts a modified regulated cascode (RGC) as input stage and the techniques of inductor peaking for bandwidth improvement thus it can operate at a low supply voltage. Under a supply voltage of 0.8 V, 50 dBΩ transimpedance gain and 24 GHz bandwidth are achieved with 6.7 mW power consumption and a 0.31 mm2 chip area.
In chapter 4, two 40-Gb/s transimpedance amplifiers are realized in 90 nm CMOS. The first one adopts a modified regulated cascode (RGC) as input stage and the technique of reversed triple resonance network (RTRN) for bandwidth enhancement thus it can operate at a low supply voltage. Besides, using the technique of three-dimensional inductors, the chip area is substantially reduced. Under a supply voltage of 0.8 V, it can obtain a 50.3 dBΩ transimpedance gain, 29.6 GHz bandwidth with 7.6 mW power consumption and a 0.23 mm2 chip area. The second design uses a common-gate configuration as the input stage and the technique of reversed triple resonance network (RTRN) for bandwidth enhancement and low voltage operation. Similarly, the chip area is substantially reduced by using 3-D inductor. This topology leads to a higher bandwidth, lower input-referred noise and lower power consumption than the RGC input stage. Under a supply voltage of 0.8 V, it can obtain a 50 dBΩ transimpedance gain, 30.8 GHz bandwidth, 4.1 mW power consumption and 0.23 mm2 chip area.
In chapter 5, we will give the conclusions with the recommendation of future works.
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