| Summary: | 碩士 === 國立清華大學 === 電子工程研究所 === 103 === Nowadays, due to the benefits of its high program efficiency, low power consumption, and over-erase immunity, split gate flash cells are widely used in both stand-alone products and embedded applications. However, the asymmetric structure of spilt gate device limits the memory array arrangement. The high density array arrangements, such as AND and NAND, are not suitable for the conventional logic-based embedded spilt gate flash technology. In this thesis, we propose a novel AND split gate flash (ASG) to realize two-bits per cell operation in 0.18 μm embedded memory technology. By device and process optimization, this cell can operate at highly efficient source side injection (SSI) and FN-tunneling mechanism for program and erase, respectively. The electrical analysis shows fast program speed and good endurance. Besides, excellent disturb immunity and data retention at 150℃ for 1000 hours further prove its superior reliability.
This unique cell can be arranged in AND-type array, reducing 50% cell size compare to conventional spilt gate flash. In this study, a highly density 3Mb AND-type Split Gate Flash Memory array chip is successfully demonstrated in 0.18 embedded flash technology. This new cell featuring high density, large read window and outstanding reliability is one of the promising solution for flash applications.
|
|---|
