| Summary: | 碩士 === 國立清華大學 === 電子工程研究所 === 103 === Semiconductor manufacturing technology has followed the prediction of Moore’s Law in past decades, and the size of transistors scaled down continually. To overcome the issue of leakage current and the on current level, researchers come up with new structures and process method. In the CMOS logic process under 20nm, we change to 3D structure which has gate covering the fin. We can make the depletion region fully surround the substrate in FinFET structure, and this design leads to low leakage current and excellent gate control. It is advantage to scale down the device.
When the thickness of gate dielectric scales down, the method to detect the antenna effect needs to be changed. We can connect the gate to metal layer which has big area, and observe the subthreshold swing, threshold voltage, transconductance and TDDB results of the transistor. And we can use these parameters to detect the influences of antenna effect. Also, we can use some measurement skills to detect the plasma induced damage. For example, C-V measurement, gate leakage current measurement. But as the dielectric thickness scales down, the FN leakage current will go through the dielectric directly, and the damage will not show in the parameters of transistor, and we will underestimate the damage due to antenna effect. So we need another methods or devices to trace the plasma induced damage.
In this paper, we propose a structure using contact coupling floating gate, and we use it to pass the high voltage to floating gate to attract the charges from substrate in the plasma process. We can store the charges in the floating gate and quantitatively and qualitatively analyze the damage due to plasma charging. This device can be used as the test pattern on the wafer in the processes. We can put it on the different locations and connect it to different metal layers. Researchers can detect the damage on time and focus on the issue by simple measurement. It will help a lot in the process of wafer.
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