Ground Bounce Reduction Scheme for Low Voltage 6T SRAM with Dual-Split-Control Assist Technique
碩士 === 國立清華大學 === 電子工程研究所 === 103
Main Author: | 張庭豪 |
---|---|
Other Authors: | 張孟凡 |
Format: | Others |
Language: | zh-TW |
Published: |
2014
|
Online Access: | http://ndltd.ncl.edu.tw/handle/04492825694464736068 |
Similar Items
-
A New Dual-Split-Control-Assist 6T SRAM with Improved Vmin and Access Speed
by: WANG, HAO-PING, et al.
Published: (2019) -
Dual Threshold Voltage SRAM & BIST Comparators
by: Po-Ming Lee, et al.
Published: (2004) -
Synchronous/Asynchronous 4-T SRAM Using Dual Threshold Voltage
by: Hon-Yuan Leo, et al.
Published: (2002) -
A Reliable Leakage Reduction Technique for Approximate Full Adder with Reduced Ground Bounce Noise
by: Candy Goyal, et al.
Published: (2018-01-01) -
28nm Low Voltage 6T SRAM with Lower Power Consumption Assist Circuit Design
by: LIU, ZHI RONG, et al.
Published: (2017)