On Reducing Wirelength in Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs
碩士 === 國立清華大學 === 資訊工程學系 === 103 === Since the implementation of true 3D ICs is still problematic, interposer-based 3D ICs (or known as 2.5D ICs) has been seen as an alternative approach. In a 2.5D IC, the floorplan of dies on the interposer and the signal assignment of macro-bumps and TSVs would im...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/91716356202676196748 |