A Receiver with Common Mode Voltage Regulation and LeakageProtection for FlexRay Systems and Slew Rate Self-Adjusted2×VDD Output Buffer with PVTL Compensation
碩士 === 國立中山大學 === 電機工程學系研究所 === 103 === This thesis is mainly aimed at circuit designs for communication interfaces, including two topics, namely a receiver with common mode voltage regulation and leakage protection for FlexRay systems, and slew rate self-adjusted 2×VDD output buffer with PVTL compe...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/759y48 |