A Receiver with Common Mode Voltage Regulation and LeakageProtection for FlexRay Systems and Slew Rate Self-Adjusted2×VDD Output Buffer with PVTL Compensation

• Main Authors: Kai-wei Juan, 阮開威
• Other Authors: Chua-Chin Wang
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/759y48

碩士 === 國立中山大學 === 電機工程學系研究所 === 103 === This thesis is mainly aimed at circuit designs for communication interfaces, including two topics, namely a receiver with common mode voltage regulation and leakage protection for FlexRay systems, and slew rate self-adjusted 2×VDD output buffer with PVTL compensation. The first design is a receiver with common mode voltage regulation and leakage protection for FlexRay systems. It consists of a common-mode voltage adapter circuit, an over-voltage protector and a decision circuit. The input range of the voltage adapter circuit is clamped to -10 V to +15 V. The over-voltage protector ensures the system to sustain ±60 V surges on the input lines. The current state of receiver is determined by the Decision circuit. The second topic is a slew rate self-adjusted 2×VDD output buffer with PVTL compensation.With proposed PVTL compensation, the driving current of output stage is automatically adjusted. When the slew rate drops, extra paths of charging and discharging will be turned on. By contrast, if the slew rate goes up, certain paths of charging and discharging will be closed. The variation of the slew rate is justified to be reduced.