Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System
碩士 === 國立中山大學 === 電機工程學系研究所 === 103 === This thesis describes the design and evaluation of an integrated circuit (ASIC) implement eight parallel signal channels providing analog-amplitude delay-and-add functionality. This implementation is a fundamental building block towards the future realization...
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| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/53357531533440958940 |