Multi-channel Delay-Line ASIC with Variable Delays towards a VSR System

• Main Authors: Sheng-Chih Chuang, 莊勝智
• Other Authors: Robert Rieger
• Format: Others
• Language: en_US
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/53357531533440958940

碩士 === 國立中山大學 === 電機工程學系研究所 === 103 === This thesis describes the design and evaluation of an integrated circuit (ASIC) implement eight parallel signal channels providing analog-amplitude delay-and-add functionality. This implementation is a fundamental building block towards the future realization of a low-power velocity-selective-recording arrangement (VSR) for the processing of the peripheral neurogram. The system is intended to operate with preamplified nerve signals acquired in the true-tripole configuration using an implanted nerve cuff. The matched velocity and sample rate are controlled by externally supplied digital clocks. The ASIC contains the clock phase generators (which use the suppliedclocks as reference), four capacitance-based sample-and-hold sections each consisting of eight sampling cells with summation functionality, an output buffer, and supporting control units. The circuits were fabricated in TSMC 0.35 μm CMOS technology. Two slightly different versions of the integrated system are reported. The second version adds an on-chip frequency divider to achieve more finely controlled sample settings and it improves the layout. The active area is about 850 μm*450 μm and 640 μm*390 μm respectively. Both systems are evaluated in transistor-level simulation. Moreover, bench test measured results for the second version system are presented which confirm the correct operation of the on-chip generated timing signals and a measured power consumption of 170 μW using a 3.3V supply.