A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC
碩士 === 國立中山大學 === 資訊工程學系研究所 === 103 === This thesis presents the architecture of a 10-bit 250-MS/s two-step pipelined analog-to-digital converter for reducing power consumption in TSMC 90nm CMOS technology. The first stage is implemented with a 5-bit binary search ADC to increase conversion speed. T...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/b574m9 |