| Summary: | 碩士 === 國立中山大學 === 資訊工程學系研究所 === 103 === This thesis presents the architecture of a 10-bit 250-MS/s two-step pipelined analog-to-digital converter for reducing power consumption in TSMC 90nm CMOS technology. The first stage is implemented with a 5-bit binary search ADC to increase conversion speed. The second stage is built with SAR ADC which can enhance the accuracy of the entire system. In order to achieve high speed of the second stage, a concept of two-channel time-interleaved is adopted.
In BS-ADC, we use the mechanism of predicting reference voltage in switching circuit to reduce the number of comparator efficiently. The 2nd stage ADC receives the result from 1st stage ADC bit by bit and directly switches the matching capacitor. The method can reduce settling time for switching capacitor and lower settling error. In SAR ADC, we proposed a method that connects the bottom of LSB capacitor to half reference voltage. Compared to the conventional architecture, the total capacitance is reduced by 75%. Therefore, it can get the small area and fine power efficiency.
|
|---|
