| Summary: | 碩士 === 國立中山大學 === 資訊工程學系研究所 === 103 === Ray-tracing can render more realistic images than the traditional depth-buffer based rendering approach such that many people expect it can be gradually applied to embedded applications in near future. However, the computational complexity of ray-tracing rendering is very high such that it can hardly be realized by pure
software implementation. Therefore, this thesis proposed a dedicated ray-tracing hardware design. The proposed ray-tracing circuit is mainly composed of a traversal unit, an intersection unit, and a shadow-ray generator. For ray-tracing rendering, the graphics objects are usually represented in a tree structure in order to reduce the overall number of intersection tests. Therefore, the tree-traversal operation becomes a critical part of the entire ray-tracing process. In this thesis, a new travel unit has been proposed which is based on hybrid single and packet ray traversal technique. Packet-ray traversal can be used to reduce the ray-box intersection tests, but for those packets whose rays do not have good coherence property, it may lead to the increase of the ray-triangle intersection tests. Therefore, in our thesis, the primary rays and shadow rays will be traversed in packets, while the other secondary rays will be traversed individually.Our results show that the proposed hybrid traversal can save more than half of cycles compared with single ray traversal. It can still save more than 40% of executions cycles compared with pure packet-ray traversal. The saving may increase when more secondary rays are generated in the scene. Our ray-tracing circuit has been verified in a SOPC (System-on-a-Programmable-Chip) platform. The overall gate count is 720 K, and can run up to 161 MHz under 90 nm technology.
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