Design of an Algorithmic Router for 3D On-Chip Networks with Irregular Topologies

• Main Authors: Fang-Bin Liou, 劉芳賓
• Other Authors: Hsin-Chou Chi
• Format: Others
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/17425631705985214402

碩士 === 國立東華大學 === 資訊工程學系 === 103 === With rapid advance of IC technology and computer system design, chip design is more and more complex. Nowadays, we can put tens or even hundreds of silicon intellectual property (IP) cores in a single chip as system-on-chip (SoC). However, with the physical restriction of chips, Moore Law is no longer applicable in the near future. Hence, 3D chips have been proposed to overcome the problems. With 3D chips, the interconnect between IP cores is even more challenging than 2D chips. Recently, network-on-chip (NoC) architectures have been proposed for the interconnection framework in SoCs. The on-chip networks for 2D and 3D chips can potentially provide a high-performance, low-cost, and robust interconnection system for such complex SoCs. This thesis proposes the design and implementation of a router for 3D on-chip networks. Our router can be associated with each IP core and used each tile in NoC. Such design can be employed in on-chip networks with regular mesh topology or even irregular mech topology. Our routing design, called the elevator-based TRAIN (EBT), is a modified routing scheme of our previously proposed TRAIN, and can be used for efficient routing in 3D NoCs with over-size IP cores. The EBT is deadlock-free and reqires no routing table in the routing switch. It provides high-performance and low-cost on-chip communication for 3D chips. We have implemented our router as an IP core using TSMC 90ns technology. The results show that our design is feasible and provides good cost performance.