Design of Tree-Based Shortcut Routing for 3D On-Chip Networks with Over-Size IP Cores

• Main Authors: Tai-Yi Chou, 周泰伊
• Other Authors: Hsin-Chou Chi
• Format: Others
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/09080407878044853465

碩士 === 國立東華大學 === 資訊工程學系 === 103 === With the rapid advance of chip manufacturing technology, more and more functions and modules can be integrated into a single chip. Nowadays, tens or hundreds of silicon intellectual property (IP) cores can be put in a chip. Such system-on-chip (SoC) design, however, requires a high-performance and low-power on-chip interconnects to provide efficient communication within SoCs. Recently, network-on-chip (NoC) architectures have been proposed for such interconnection framework in SoCs. Furthermore, as Moore's Law cannot keep valid a few years from now, 3D chips have been proposed and studied for future development of chip manufacturing. The internal interconnect for 3D chips will be even more critical for the system chips with 3D technology. This thesis proposes the routing algorithm and architecture for the NoC in future 3D chips. We focus on the routing techniques for the 3D mesh network with over-size IP cores. In such networks, the network topology is no longer a regular mesh with unit-size IP cores. Although some researchers have proposed their routing algorithms for the regular and homogeneous 3D mesh network. These routing designs do not work on more irregular networks with over-size IP cores. Besides, some other researchers employed look-up routing table for irregular networks. However, their routing algorithms require costly routing tables in the routing switch. Our routing design, called the elevator-based TRAIN (EBT), is a modified routing scheme of our previously proposed TRAIN, and can be used for efficient routing in 3D NoCs with over-size IP cores. We show that the EBT is deadlock-free and requires no routing table in the routing switch. It provides high-performance and low-cost on-chip communication for 3D chips. We evaluate the performance of the EBT by running many simulations with the Booksim simulator, and compare it with other routing designs. Both uniform and hot-spot traffic patterns are simulated for various 3D network topologies. The results show that the EBT achieve superior performance to the other designs, especially when the routing switch has more than two virtual channels at each input port.