| Summary: | 碩士 === 國立中央大學 === 電機工程學系在職專班 === 103 === In recent years the performance and speed of VLSI circuits grew up with
scale-down process, and now the chip changes to integrate SOC. There is often
phase error or clock skew which generate asynchronous phenomenon in
different sub-circuit blocks. The different phase of operate clock that
caused to output data error in integrate system. Hence, it needs Phase-Locked Loop
(PLL) for decreasing phase error that make the clock phase is corresponding
in order to decrease output data error in sub-circuit of integrate system.
The key point is to decrease the jitter of PLL output signal. The high linearity
of Voltage-controlled Oscillator(VCO) achieves the goal.
In this thesis, a wide band PLL with a high linearity voltage-controlled
oscillator(HLVCO) in full range is proposed. How to achieve a HLVCO ? A idea is
the beginning. Then validate the correctness of the HLVCO characteristics:
f=KvcoVctrl+fmin by theoretic derivation. The key point is the performance of
VCO bias circuit in the overall develop process. That is the relations of input
voltage Vctrl and output current Ictrl of VCO bias have to be linear. In this
thesis, four bias architectures achieving linear requirement are presented. First
choose a best one from analyzing their advantages and drawbacks. Then from the
process of design, simulation to validate the best one posses good features of
full range operation, wide band and wide voltage. In the basis a multi-band HLVCO
in full range operation is constructed. Finally a PLL is developed in this thesis.
It produces five low jitter output phases achieving the goal of low output jitter
mentioned previously. In the different process corners and temperatures the
frequency range of 80MHz~160MHz is locked correctly.
We use the CIC CMOS 0.18um 1P6M virtual process with supplying 1.8V voltage
in proposed PLL. The temperature range is 0℃ ~ 75℃. The reference input frequency
range is 5MHz~10MHz and the output frequency range is 80MHz~160MHz. The jitter
of output frequency is 19.2ps~18.1ps (pk-pk). The lock time is 51.5us~49.1us and
the power consumption is 1.86mW~3.29mW.
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