High Matchability Capacitor Array Placement with an Accurate Mismatch Model

• Main Authors: PingYang Cheng, 程平洋
• Other Authors: Chien-Nan Liu
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/64955409124496924285

碩士 === 國立中央大學 === 電機工程學系 === 103 === The usage of analog-to-digital converters (ADC) and digital-to-analog converters (DAC) is very important in many VLSI designs. These two devices connect other logic-related devices to the real world and turn into the technologies we are using today. However, during fabrication process, the capacitors in ADCs and DACs suffer from mismatch induced error which may stop the ADCs and DACs from functioning properly. To solve the problem, we proposed a new capacitor array placement method to determine how the capacitors in ADCs and DACs should be placed. An accurate mismatch model is also proposed to estimate the mismatch induced error among the capacitors before ADCs and DACs are fabricated. With the new method and mismatch model, the experimental result showed that 13% increasing in matchability compared with the state-of-the-art method.