| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 103 === Due to the sensitivity of analog components, both post-layout non-ideal effects and reliability are getting important with the size shrink of components. In order to reduce the impact of non-ideal effects on circuit performance and increase the reliability, the layouts of analog circuits are often generated manually. Although some EDA tools based on designer experience are available now to reduce design efforts, the complex layout constraints are still big issues for developing EDA tools.
There are many literatures on analog placement, but the number of researches on analog placement considering both reliability and routing are few. In order to reduce the impacts on the layout caused by the process variations and non-ideal effects, topology constraints are often used to reduce the mismatch between devices. However, the non-ideal effects may still exist in the routing paths. In order to reduce the impacts from routing paths on reliability and circuit performance, narrow wires, right-angle corner bend and long wires should be avoided in the routing paths. It implies that preserving routing space accurately during placement stage is required to ensure the performance and lifetime of the circuits.
This work presents an analog placement flow for analog circuits with reliability consideration. First, proper routing space is preserved for routing paths, corner bends and wide wires. Then, a two-stage curve pruning technology is proposed to obtain the placement results with shorter wire-length and smaller area. Finally adopting deferred decision making (DDM) technique, multiple flexible solutions can be provided for designers.
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