Efficient Algorithms for Constant Multiplications and Their Hardware Implementation

• Main Authors: Ping-Chang Jui, 鞠萍章
• Other Authors: Chin-Long Wey
• Format: Others
• Language: en_US
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/13117409044134393249

博士 === 國立中央大學 === 電機工程學系 === 103 === Integer constant multiplier performs a multiplication of a data-input with an integer constant value. The multiplication by a fixed-point constant can be done “multiplier-less” using additions and shifts only. Since the shifters are implemented as hard-wired inter-block connections, they are considered “free.” Thus, the number of adders determines the implementation cost. The integer constant multiplication is a common operation in digital signal processing (DSP) algorithms with the following applications: digital signal processing, image processing, multiple precision arithmetic, cryptography, etc. It can also be applied for the arithmetic coding technique, such as AN code for information redundant design, Booth encoding technique for multiplications, and high-radix SRT division, etc. Constant multiplier designs have been investigated for several decades. However, the emphasis was placed on minimizing the number of additions required to achieve the multiplications with single constant or multiple constants. Moreover, the types of adders to be implemented are not of concern. This motivates to this study developing efficient algorithms and hardware implementation for fast constant multiplications. This study focuses on the development of fast multiplications of the constants in the form of (2^k+-1). The value of (2^k+1)N can be computed by adding N to its k-bit left-shifted value 2^kN. On the other hand, the value of (2^k-1)N can be computed by subtracting N from its k-bits left-shifted value 2^kN, or adding (-N) to 2^kN. The fast unit cells for additions (UCAs) are introduced to construct the UCA-based adders. The proposed UCA cells requires only one gate delay, while the conventional full adder (FA) needs two gate delays. Simulation results will show that the proposed UCA-based adders, such as ripple carry adders (RCAs), carry lookahead adders (CLAs), and hybrid RCA/CLA adders (HyAs), achieve faster speed performance with reasonably small hardware cost than the FA-based ones. The UCA design concept is readily applied to the multiplications with the constants in other forms.