An Ultra-fast Response and Low Power Consumption Digital Low Dropout Regulator for High Speed embedded Memory Applications

• Main Authors: Chen, Jui-Lung, 陳瑞隆
• Other Authors: Chen, Ke-Horng
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/g86zt2

碩士 === 國立交通大學 === 電機學院電機與控制學程 === 103 === This work discussed and achieved digital low dropout (LDO) regulator with the advantage of ultra-fast response and low power consumption for embedded memory applications. Conventional analog LDO regulator needs to use large de-coupling and phase-compensation capacitors to keep low transient dip voltage in case of loading current change and system stability, respectively. Another issue is transient response of analog LDO is much slower than that of embedded memory applications. That is to say, analog LDO regulator is kept active to have the ability to react to fast response of memory applications. Consequently, light-load power efficiency drops substantially. This paper presented digital LDO (DLDO) regulator to meet the requirement of high-speed embedded memory applications due to its features of ultra-fast response and low power consumption. Thus, large de-coupling capacitor is not needed to prevent large voltage change. De-activating DLDO regulator can save much power when memory macro enters standby mode. The major circuit design of DLDO includes three parts, voltage reference generator, power switch, and timing control block. Voltage reference generator is constructed by a sub-threshold voltage bias circuit to generate reference voltage and supply current to memory macro at standby mode. Power switch is constructed by two MOSFETs to switch on/off according to memory operating mode. Timing control block combines clock-controlled latch type comparator, shift-register block, and variable capacitance capacitor, which is controlled by system clock. System clock will activate comparator to control shift-register to change on time of power switch. To verify this work in VIS 0.16μm HV process, conventional analog LDO and DLDO with embedded SRAM macro. A mixed-mode tester is designed for microprocessor unit (MCU) with universal serial bus (USB) front-end and 40 input/output (IO) ports to control SRAM Read/Write and to measure current flow and voltage change. Experimental results showed improved performance of the proposed DLDO compared to conventional analog LDO. All specifications needed by memory macro can be correctly met.