| Summary: | 碩士 === 國立交通大學 === 電機工程學系 === 103 === Phase-locked loops (PLLs) are widely used for SOC applications, such as Clock and Data Recovery (CDR) and wireless communication systems. In the early development of PLL, PLL design was realized by analog approach. However, with the process technology scaling down, analog circuits need to be redesigned. In additional, analog PLL circuits use passive components, which occupy lots of area, and the speed of analog PLL circuits is usually slower than that of digital PLL circuits. ADPLLs have becomes popular in recent years.
In this thesis, we implement the ADPLL by using full-custom design flow. In the first chip, we propose an innovative multi-stage TDC and a Time Amplifier to achieve 1ps resolution. The Time Amplifier with calibration circuit generates precise amplification. The proposed DCO with a linearly periodic digital-to-frequency relationship operates 140MHz to 1220MHz. In the second chip based on the first chip, a Frequency Tracking Engine (FTE) and Interpolation DCO are introduced to reduce the locking time and increase the resolution of DCO, and the operation range is from 150MHz to 1450MHz.
Both of chips we designed to locked at 800MHz. The measurement results show that the first chip has a peak-to-peak jitter of 21.67ps. The ADPLL has an area of 0.1845mm2, and the power dissipation of 21.32mW. For the second chip, there are post-simulation value of 21.9ps peak-to-peak jitter and the power dissipation of the ADPLL is 18.2mW.
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