A Fast-Locking All-Digital PLL with 1ps resolution TDC using Calibrated Time Amplifier and Interpolation DCO
碩士 === 國立交通大學 === 電機工程學系 === 103 === Phase-locked loops (PLLs) are widely used for SOC applications, such as Clock and Data Recovery (CDR) and wireless communication systems. In the early development of PLL, PLL design was realized by analog approach. However, with the process technology scaling dow...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/54mxzm |