NaDaP:TSV Noise-Aware &; Density-Aware Placement for 3-D ICs

碩士 === 國立交通大學 === 電信工程研究所 === 103 === In this work, we proposed a TSV noise-aware &; density-aware technique based on force-directed placement to reduce total noise and maximum peak noise of TSV in 3-D IC global placement stage. The peak noise value, which may lead to function errors in digital...

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Bibliographic Details
Main Authors: Pan, Kuan-Te, 盤冠德
Other Authors: Lee, Yu-Min
Format: Others
Language:en_US
Published: 2015
Online Access:http://ndltd.ncl.edu.tw/handle/k7qqck
Description
Summary:碩士 === 國立交通大學 === 電信工程研究所 === 103 === In this work, we proposed a TSV noise-aware &; density-aware technique based on force-directed placement to reduce total noise and maximum peak noise of TSV in 3-D IC global placement stage. The peak noise value, which may lead to function errors in digital circuit design is relative to the TSV distribution in die area. In previous works, the decoupling forces are used to reduce the total noise of TSVs, and the rough legalize forces are used to improve the cell overlap. Then, we introduce the density force to adjust the TSV density. The main idea of TSV density force is trying to push the TSVs in high density bin to low density bin. In all experiments, the TSV coupling force combine with TSV density force effectively reduces the maximum peak noise for 42.6% and the total noise for 15.0% in average and causes only 4.6% wirelength overhead compared to wirelengh-driven placement, moreover, compares with the result of decoupling forces only placement, the total noise and the maximum peak noise are 4.4% and 26.4% smaller respectively, and the wirlength is 0.9% shorter.