Design of 5.2-GHz Linearity-Enhanced Power Amplifier and Gain-Boosted Up-Conversion Mixer

• Main Authors: Chen, Nai-Chang, 陳乃菖
• Other Authors: Wu, Lin-Kun
• Format: Others
• Language: en_US
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/89290381492568803151

碩士 === 國立交通大學 === 電信工程研究所 === 103 === This thesis focuses on the design of a power amplifier (PA) and an up-conversion mixer for IEEE 802.11a application. The circuit designs and chip fabrications are all implemented in TSMC 0.18-μm mixed-signal/RF CMOS 1P6M technology. 　　When designing the power amplifier, a cascode architecture is adoped, and linear power amplifier is chosen for the sake of linearity requirements. But instead of using conventional types such as Class-A, Class-AB, Class-B and Class-C, this circuit combines a Class-A and a Class-B together in parallel, and biases the Class-B with a diode-connected NMOS. These two methods both have the effect of extending the P1dB. In addition, this circuit uses a self-biasing technique in the common-gate stage of the cascode, therefore improving the output power and the efficiency. The simulation results show that with a 3.3V power supply, the proposed PA provides a gain of 10.4 dB, an output 1-dB Gain Compression Point (OP1dB) of 23.1 dBm with 25.5 % power add efficiency (PAE), a maximum PAE of 27.7 %, and delivers a maximum output power of 24 dBm. The OIP3 is 35.4 dBm, and the DC power consumption is 514.8 mW. 　　When designing the up-conversion mixer, the circuit implements a cross-coupled pair in the transconductance stage. This method can enhance the conversion gain with only a little extra DC power consumption and without sacrificing the linearity. The simulation results show that with 5.2 GHz RF frequency, 100 MHz IF frequency and 5.1 GHz LO frequency, the conversion gain is 8.4 dBm, OP1dB is 0.3 dBm, OIP3 is 12.4 dBm, and the power consumption is 5.9 mW.