| Summary: | 博士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === 3D NAND Flash architecture will replace the traditional planar NAND Flash as the mainstream of the next generation NAND Flash technology. The drive force to develop 3D NAND Flash technology is the continuing cost down per bit by increasing the memory layers stacking. In the technology development history of 3D NAND Flash, the first generation 3D NAND Flash architecture is not economic because of its copious process flow in fabricating each memory layer. Then, the concept, Multiple Layers Stack and One Critical Cut, creates the milestone in the secondary generation. The representative technology is Bit-Cost Scalable technology (BiCS). In this generation, the multiple memory layers are stacked vertically and one critical etch process formats each memory cell separately. Henceforward, plenty of 3D NAND Flash architectures are proposed and some of them are mature enough to manufacture the NAND Flash products.
Since each 3D NAND Flash technology has its specific merits and demerits, a systematic analysis is investigated in Chapter 2. The fair comparison is done with the well definition of the horizontal and vertical pitches by using TCAD simulator. It also analyzes the merits and demerit among 3D NAND architectures in detail. The horizontal current flow approach such as Vertical Gate (VG) architecture has its benefit in the memory layers stacking and the horizontal pitch scaling while the vertical current flow approach suffers the current degradation and the pitch scaling limitation beyond 50nm.
The worst case in these 3D NAND architectures is the Vertical Stack Array Transistor (VSAT) technology. The multiple U-turn current flow and single gate structure perform the worst cell characteristic. To improve its disadvantages, the asymmetrical WL cut process and the top and bottom assisted gate approaches are proposed. These processes will be introduced in Chapter 3. From the simulation results, not only the bit density is improved by applying the asymmetrical WL cut process but the cell performance becomes better with the aid of the assisted gate structure.
In 3D NAND architectures, poly-Si material replaces the crystal silicon as the conduct channel material. Though this approach provides the process flexibility, the electrical characteristic degrades due to the randomly distributed grain boundaries and grain boundary traps. In Chapter 4, TCAD simulator is applied to create the environment about the randomly distributed grain boundaries with its corresponding traps. By comparing the experimental and simulation results, the cell performance degrades severely with the heavier grain boundary conditions. Drain induced grain barrier lowering (DIGBL) effect and gate induced grain barrier lowering (GIGBL) effect are two specific phenomena in the poly-Si thin-film transistor. In the application of the DIGBL effect, the decisive grain boundary location with its traps can be examined by applying the read voltage at the drain side or source side. This method can be applied to locate the main grain boundary barrier.
Another specific phenomenon in 3D NAND Flash technology is pass gate voltage interference (Vpass interference). In the 3D NAND Flash process integration, it is not easy to form the doped junction between WLs and the junction-free structure is naturally formatted. To read through the selected memory cell, the suitable pass gate voltage is applied in the WLs’ except the selected one. The fringing field from the adjacent WL forms the virtual junction under the space region and the electrons can flow from source to drain. However, this fringing field also penetrates into the selected WL to affect its cell performance. This situation becomes worse with the pitch scaling. This topic will be studied by comparing the experimental and simulation results in Chapter 5.
In this dissertation, a general overview to understand 3D NAND Flash technology development is obtained at first. The imperfect 3D NAND Flash technology is studied extensively and improved significantly. In the fundamental study, the impact of the randomly distributed grain boundary and its traps are studied in detail. Pass gate voltage forms the virtual junction inside NAND Flash, but the fringing field also induces the Vpass interference. After evaluating them, an in-depth understanding in 3D NAND Flash is obtained. Several future works will be also introduced in Chapter 6.
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