A Parallel Mixed-Radix Feedforward FFT Processor for 4G Communication System

• Main Authors: Tsai, Wei-Lun, 蔡維綸
• Other Authors: Chen, Sau-Gee
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/28536805993848607314

碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === The multi-carrier modulation method called OFDM (Orthogonal Frequency Division Multiplexing) [1], for examples: WLAN (Wireless Local Area Network) ,LTE (Long Term Evolution) and forth generation (4G) communication system (LTE-A). And DFT (Discrete Fourier Transform) is the most critical component in implementing an OFDM system. In 1965, JW Cooley and John Tukey published the Cooley-Tukey algorithm , which is well known as FFT (Fast Fourier Transform) algorithm. This algorithm significantly reduces the computational complexity and hardware cost required for DFT operation and becomes one of the key reasons why OFDM/OFDMA modulation can be widely used with relatively low complexity. Since recent years, as a result of increasing requirements of mobile devices, particularly the data transmission rate, FFT/IFFT processor design has become more and more challenging, The concerned important design issues include power consumption, area complexity, throughput, reconfigurable design and multi-standard supporting. This thesis presents several FFT design challenges in the fourth-generation mobile communications systems and corresponding solutions as follows: In order to reduce the hardware complexity of FFT processor, this thesis proposes a novel ROM-less twiddle factor multiplication scheme and architecture that can be used in non-power-of-two FFT processor. With the help of techniques such as CSD (Canonical Signed Digit) encoding and Sub-expression sharing, high area complexity problem occurred in conventional complex multiplier plus ROM design is solved with proposed rotator. The rotator design method has the advantage of supporting multi-standard OFDM systems, it is reconfigurable and can be applied to any other FFT processor. A feedforward Radix-3 BU (Butterfly Unit) and parallel 2k×3-point FFT architecture are presented. Those design methods are applied to the FFT processors for 4G communication system so as to achieve the goal of low-area complexity, high parallelism and high throughput rate.