| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === High Efficiency Video Coding (HEVC) is the state-of-the-art video coding standard, which improves greatly compression performance relative to H.264/AVC, but its advanced techniques lead to high encoding complexity. Especially, the motion estimation (ME) in HEVC accounts for more than 50% encoding time. This thesis presents four techniques to reduce the computational complexity for HEVC. We first analyze motion activity of advanced motion vector prediction (AMVP) to skip the ME computations of non-square prediction units (PUs). Secondly, we create a skipping map to skip unnecessary ME and set zero to motion vector (MV). Thirdly, we employ an enhanced cross-hexagonal-inner search pattern to reduce search points. Fourthly, we set a rate-distortion cost (RD cost) threshold in search center to early terminate the ME computation. The proposed techniques have been implemented in HEVC reference software HM 10.0 and the experimental results show that approximately 97.96% of search points for ME are saved, while the Bjontegaard Distortion-rate (BD-rate) is only increasing by 0.6%. Finally, we design the hardware architecture composed of 3 cores IME engine to implement our proposed algorithm. The proposed IME engine is implemented by TSMC 90nm technology. Overall ME architecture employs 3 cores of the proposed IME engine and gate counts of each IME engine are only about 20.3K. The maximum working frequency is 238MHz, can supports 4Kx2K 30fps in real time video coding.
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