| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === This thesis investigates monolithic 3D logic circuits and 6T SRAM composed of InGaAs-n/Ge-p MOSFETs considering interlayer coupling. We have compared the 3D results with the 2D counterparts, and have compared the InGaAs/Ge results with the Si counterparts. In addition, we have investigated the impact of interlayer coupling for 3D 6T SRAM with high/low threshold voltage design, and have shown enhanced performance by replacing Si CMOS with InGaAs/Ge CMOS.
TCAD simulation results indicate that monolithic 3D InGaAs/Ge inverter and 2-way NAND can improve the performance while maintaining equal leakage with 2D counterparts through optimized layouts. Similarly, 3D InGaAs/Ge 6T SRAM can simultaneously improve the stability and cell performance while maintaining equal leakage with 2D counterparts through optimized layouts. We have also suggested two layouts for 3D 6T SRAM for high performance and low power operation, respectively. Moreover, compared with the Si counterparts, InGaAs/Ge logic circuits and 6T SRAM cell exhibit larger performance enhancement of 3D over 2D designs.
For Si 6T SRAM with different threshold voltage (VT) designs, monolithic 3D structure can enlarge the RSNM advantage of high VT design and reduce the gap in cell performance between high/low VT designs. Moreover, replacing Si CMOS with InGaAs/Ge CMOS can improve the 6T SRAM cell performance. Monolithic 3D InGaAs/Ge high VT SRAM can improve the cell performance and WSNM while maintaining comparable RSNM as compared with the Si counterparts.
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